| 摘要 |
An electronic circuit contains a phase locked loop. The phase of a frequency divided output signal of a controllable oscillator is compared with the phase of a reference signal and the result of the phase comparison is used to control the frequency of the controllable oscillator. Frequency division is by time-varying integer division ratios, so that the integer division ratios on average substantially equal a nominal division ratio. The loop contains a variable delay circuit coupled between the controllable oscillator and the input of the frequency divider. Delays of the delay circuit are controlled so that the delays prevent deviations between period lengths of the output signal of the divider. The period lengths are made equal to period lengths of a notional signal with a frequency equal to the frequency of the oscillator divided by the nominal division ratio.
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