| 摘要 |
The invention relates to a computer system which can tolerate transient errors and which consists of a processing unit, comprising the following: at least two processing units (50, 51), each comprising a microprocessor (54, 57), a memory (53, 56) that is protected by a device that generates and checks an error detection and correction code and a device (55, 58) for surveying memory access; a centralised device (52) for managing the processing units and the inputs/outputs, comprising the following: macro-synchronisation means, data comparison/election means, correction request means, decision-making means and means for effecting the inputs/outputs; and links (60, 61) connecting each processing unit to the device (52) for managing the processing units and the inputs/outputs, respectively.
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