发明名称 |
Method of designing and structure for visual and electrical test of semiconductor devices |
摘要 |
In a semiconductor device using fill shape patterns incorporated into wiring levels to increase the planarity of the wiring levels, the fill shapes are aligned from one wiring level to another wiring level to provide lines of sight to lower wiring levels for visual inspection. Also, in accordance with the invention, selected aligned fill shapes are interconnected with vias to form conductive stacks for contacting lower wiring level conductive wires from upper wiring levels in order to perform electrical test probing/diagnostics.
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申请公布号 |
US6251773(B1) |
申请公布日期 |
2001.06.26 |
申请号 |
US19990473635 |
申请日期 |
1999.12.28 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
HARTSWICK THOMAS J.;MASTERS MARK E. |
分类号 |
H01L23/522;H01L23/58;(IPC1-7):H01L21/476 |
主分类号 |
H01L23/522 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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