| 摘要 |
A microprocessor capable of predecoding variable-length instructions and storing them in a three-dimensional instruction cache is disclosed. The microprocessor may comprise a predecode unit, an instruction cache, and an address translation table. The predecode unit receives variable-length instructions from a main memory subsystem. These instructions are then predecoded by detecting instruction field boundaries within each variable-length instruction. Instructions fields that are not present in a particular instruction may be added by inserting padding constants so that the instruction matches a predetermined format having all instruction fields. The predecoded instruction is stored in the instruction cache, which may be logically and physically structured as a three-dimensional array. Each instruction is stored in the cache so that it has a fixed length in two dimensions. The address translation table maintains address translations for each instruction stored in the instruction cache. Fetch addresses are input to the address translation table and, if there is a cache hit, corresponding pointers that points to the desired instruction storage locations within the instruction cache are output. The address translation table may maintain more than one pointer for each fetch address and may also store branch prediction information. A corresponding method and computer system are also disclosed. |
