发明名称 POWER SAVE CIRCUIT AND POWER SAVE METHOD
摘要 <p>PROBLEM TO BE SOLVED: To provide a power save circuit and method capable of reducing power consumption by realizing high integration and preventing the malfunction of a clock. SOLUTION: This power save circuit is provided with a program counter 1 for outputting an instruction address at the time of executing an instruction, an instruction memory 2 for storing an instruction code corresponding to the instruction address inputted from the program counter, plural instruction decoders 3-1, 3-2 and 3-N operating in response to the instruction code, plural units 4-1, 4-2 and 4-N operating in response to a signal from each decoder, a save signal generating circuit 7 for transmitting power save signals 8-1, 8-2 and 8-N to the units at the time of executing the instruction, and a register 5 for selecting the unit operating power save at the time of executing the instruction.</p>
申请公布号 JP2001166933(A) 申请公布日期 2001.06.22
申请号 JP19990354153 申请日期 1999.12.14
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 INOTA MASAAKI
分类号 G06F1/32;G06F1/04;G06F9/30;G06F9/38;(IPC1-7):G06F9/30 主分类号 G06F1/32
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