发明名称 VITERBI DECODER AND VITERBI DECODING METHOD
摘要 PROBLEM TO BE SOLVED: To constitute a path memory with a normal RAM and to reduce the circuit scale and power consumption as Viterbi decoding for decoding trellis encoded modulated signals. SOLUTION: A trace-back part 107 traces back path selection signals PS0-PS7 stored in a trace-back memory 106 for a prescribed length. A sub set number generation part 108 uses the number ND1 of a node for passing through a maximum likelihood path obtained by trace-back and outputs an encoding bit CB and a sub set number SSNO relating to transition to the node corresponding to a trellis diagram. A selection circuit 109 selectively outputs a non- encoding bit NCB relating to the transition to the node corresponding to the sub set number SSNO.
申请公布号 JP2001168739(A) 申请公布日期 2001.06.22
申请号 JP20000286901 申请日期 2000.09.21
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KAMATA TAKEHIRO
分类号 G06F11/10;H03M13/25;H03M13/41;(IPC1-7):H03M13/41 主分类号 G06F11/10
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