| 摘要 |
<p>The number of passings of individual bits of input data through the shift register of a noncyclic digital filter is reduced to save electric power. Despread data is supplied to a 1st shift register (21) and a 2nd shift register (22) when the normal number of stages is divided into two, and both the shift registers are alternately made to perform shift operations at both the edges of a shift clock (CK). Multiplexers (MP11 - MP14) which select odd number codes among reference codes stored in a reference code register (23) while the shift clock (CK) is in an off-state and selects even number codes while the shift clock (CK) is in an on-state and multiplexers (MP21 - MP24) which select reversely are provided. The outputs of the exclusive ORs of the outputs of the respective stages of the 1st shift register (21) and the outputs of the multiplexers (MP11 - MP14) and the outputs of the exclusive ORs of the outputs of the respective stages of the 2nd shift register (22) and the outputs of the multiplexers (MP21 - MP24) are added to each other by an adder (25) to produce a correlation intensity output.</p> |
