发明名称 Communication interface between processors and semiconductor integrated circuit apparatus
摘要 In the LSI, in which a plurality of the operational units are loaded in one chip, transmission buffers are disposed associated with the operational units. Reception flags and transmission flags showing states of reception buffers are assigned to each bit of a register, which is capable of being accessed from the host processor. The transmission flags are combined into one signal using OR circuits and the reception flags are combined into one signal using AND circuits, so that the combined flags are assigned to an outer pin. At first, the access from the host processor refers to a reception flag signal and a transmission flag signal of the outer pin. Then, it reads the transmission flag register and the reception flag register, checks the states of the transmission buffers and the reception buffers to access necessary transmission buffers and reception buffers.
申请公布号 US2001004752(A1) 申请公布日期 2001.06.21
申请号 US20000736429 申请日期 2000.12.15
申请人 SUZUKI KAZUMASA;ISHIDA RYUUJI 发明人 SUZUKI KAZUMASA;ISHIDA RYUUJI
分类号 G06F15/16;G06F13/42;G06F15/17;G06F15/173;G06F15/78;(IPC1-7):G06F13/00;G06F13/38 主分类号 G06F15/16
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