发明名称 |
Clock recovery pll for ATM networks |
摘要 |
<p>The invention relates to packet switched networks, and more particularly to a circuit and a method for clock recovery in cell-relay networks, particularly ATM (Asynchronous Transfer Mode) networks offering constant bit rate services. The multimode clock recovery circuit has an embedded digital phase locked loop including an input circuit capable of generating a phase signal from at least two types of input signal. The phase signal controlling the output of the phase locked loop generates clock signals for the constant bit rate services. <IMAGE></p> |
申请公布号 |
EP1109349(A2) |
申请公布日期 |
2001.06.20 |
申请号 |
EP20000311217 |
申请日期 |
2000.12.15 |
申请人 |
ZARLINK SEMICONDUCTOR INC. |
发明人 |
SPIJKER, MENNO;JEFFERY, GEORGE |
分类号 |
H03L7/085;H03L7/087;H03L7/099;H04J3/06;H04L7/033;H04L12/70;H04Q11/04;(IPC1-7):H04L7/00;H04L12/56 |
主分类号 |
H03L7/085 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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