| 摘要 |
A switched-capacitor circuit (35), and analog-to-digital converter (50) incorporating the same, is disclosed. The disclosed switched-capacitor circuit (35) receives differential input signal voltages (Vin+, Vin-), and differential reference voltages (Vrefp, Vrefn), based upon which differential output voltages (Vout+, Vout-) are generated by way of sample-and-hold, and amplify, operations. In a larger context, such as in a pipelined ADC (50), multiple switched-capacitor circuits (35) are implemented, each receiving the differential reference voltages (Vrefp, Vrefn) from a voltage reference circuit (20). In addition to the sample clock (phi1) and amplify clock (phi2), a precharge clock (phi2') is provided to the switched-capacitor circuit (35) to connect the sample nodes (VA, VB) of the switched-capacitor circuit (35) to a midlevel voltage (Vmid), prior to the active phase of a reference clock (100 2'') connecting the sample nodes (VA, VB) to the reference voltages (Vrefp, Vrefn). As a result, the loading presented by the switched capacitor circuits (35) to the voltage reference circuit (20) is greatly reduced.
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