| 摘要 |
PURPOSE: A capacitor pattern array is provided to allow an increase in capacitance per unit cell area. CONSTITUTION: The capacitor pattern array(100), particularly in a capacitor over bit-line structure, is designed to have a shape like a parallelogram over two adjacent unit cell regions each having X in length and Y in breadth. In addition, the capacitor pattern array(100) is composed of two unit capacitor patterns arranged within the parallelogram shape and spaced apart from each other by a specific gap(120). Since the capacitor pattern array(100) utilizes a neighboring cell region, the unit capacitor pattern has an increased circumference.
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