DATA OUTPUT APPARATUS OF DDR(DOUBLE DATA RATE) SYNCHRONOUS MEMORY DEVICE

摘要

PURPOSE: A data output apparatus of a DDR(Double Data Rate) synchronous memory device is provided to achieve a high speed data output by applying all of a 2 bit prefetch method and a wave pipe line method. CONSTITUTION: According to the data output apparatus. an even register part(310) stores data of an even bank, and an odd register part(320) stores data of an odd bank. A selection part(330) outputs data from the even register part and data from the odd register part sequentially in response to a priority control signal(sose<0:2>). The first register(rdo register)(340) latches data being output from the selection part at first and outputs it by synchronizing it to a rising edge of a clock. And, the second register(fbo register)(350) latches data being output from the selection part later and outputs it by synchronizing it to a falling edge of the clock. And, an output driver(360) buffers data transferred from the first and the second register and outputs it out of a chip. .Each of the even register part and the odd register part comprises three registers to store three data through three switching devices controlled by three pipe input control signals(pin<0:2>), and the selection part comprises three multiplexers.