发明名称 |
METHOD FOR PLANARIZING INTERLAYER DIELECTRIC ON CONDUCTIVE STRUCTURE |
摘要 |
PURPOSE: A method for planarizing an interlayer dielectric on a conductive structure is provided to deposit an interlayer dielectric of which planarization is excellent without dishing, by depositing the first interlayer dielectric and planarization-etching the first interlayer dielectric, and by depositing the second interlayer dielectric. CONSTITUTION: A gate electrode layer(214) is formed on a semiconductor substrate(210). A gate spacer(218) is formed on the upper portion and the side surface of the gate electrode layer. The first interlayer dielectric(222) is deposited on the entire surface of the semiconductor substrate. The first interlayer dielectric is planarization-etched until the upper surface of the gate spacer is exposed. The second interlayer dielectric(224) is deposited on the entire surface of the substrate. The second and first interlayer dielectrics between the gate electrode layers are etched by using the gate spacer as an etch blocking layer until the semiconductor substrate is exposed. A self-aligned contact(226) is formed between the gate electrode layers.
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申请公布号 |
KR20010048534(A) |
申请公布日期 |
2001.06.15 |
申请号 |
KR19990053247 |
申请日期 |
1999.11.27 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE, SANG MIN |
分类号 |
H01L21/316;(IPC1-7):H01L21/316 |
主分类号 |
H01L21/316 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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