发明名称 |
LAYERED CAPACITOR, WIRING BOARD, DECOUPLING CIRCUIT AND HIGH FREQUENCY CIRCUIT |
摘要 |
PURPOSE: To reduce the equivalent series inductance (ESL) of a layered capacitor. CONSTITUTION: First and second through conductors 20, 21, by which a first internal electrode 14 and a second internal electrode 15 which are faced with each other and a first external terminal electrode and a second external terminal electrode are connected electrically, are arranged in such a way that magnetic fields induced by currents flowing in the internal electrodes 14, 15 are offset mutually. The arrangement pitch of the through conductors 20, 21 is designated as P (unit: mm). The total number of the through holes 20, 21 is designated as N. Then, P/N <= 0.085 is set.
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申请公布号 |
KR20010049268(A) |
申请公布日期 |
2001.06.15 |
申请号 |
KR20000020637 |
申请日期 |
2000.04.19 |
申请人 |
MURATA MANUFACTURING CO., LTD. |
发明人 |
HORI HARUO;KONDO TAKANORI;KURODA YOICHI;NAITO YASUYUKI;TANIGUCHI MASAAKI |
分类号 |
H01G4/12;H01G4/232;H01G4/30;H01L23/64;H05K1/02;(IPC1-7):H01G4/30 |
主分类号 |
H01G4/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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