Kippschaltung fuer gestoerte Eingangssignale

摘要

1305119 Data storage INTERNATIONAL BUSINESS MACHINES CORP 5 Aug 1970 [26 Nov 1969] 37697/70 Heading G4C [Also in Division H3] A data registering system comprises at least one register stage for storing binary data and controlled by a cyclically-operable control circuit to be responsive to noisy binary data signals and to latch in signals present at its input at a predetermined time within each cycle, or to be responsive to substantially noiseless binary data signals and to be latched at the predetermined time to the condition of the signal presented at its input at an earlier time in the cycle. According as a signal M is up or down, 4 bits in parallel are sent in each bit time from a magnetic core memory 13 (noiseless data) to a data processor 12 via a data selector 31 and buffer register 10, or from the processor 12 (noisy data) to the memory 13 via the selector 31 and register 10. Selector 31 merely selects the data source, 12 or 13, and inverts each bit at 40 to compensate for the fact that the inverse 0 outputs of the register 10 feed the memory 13. However, the 1 outputs of the register 10 are used for feeding the processor 12, via gates 26, so the latter incorporates inverters (not shown) to compensate for inverters 40. The register 10 is controlled by signals D, S1 produced from signals A, M, B, S. Signals A is up for the last three-quarters of each bit time, signal B is up throughout, and signal S is up for the first half of each bit time. For noisy data (M down), S1 is up and D down for the first half of each bit time, during which the register outputs track the respective register inputs D1, D2, D3, D4, whereas during the last half of each bit time (by which time the noisy data levels will have reached the correct values) S1 is down and D up so that the register outputs (fed back) are latched in. For noiseless data (M up), S1 is up and D down for the first qarter of each bit time, giving tracking as above, but during the second quarter of each bit time S1 and D are both up so that each input and its corresponding fed-back output are effectively ORed to set the respective stage, and during the last half of each bit time S1 is down and D up to give latching in as before. Fig. 4 shows details of a register stage (compare Fig. 1), multi-emitter transistors 69, 70, 71 being ANDs 18, 19, 20 respectively, transistors 72, 73, 74 being OR 21, transistor 75 being inverter 22, and transistors 79, 80, 81 being inverter 23.