Clock synchronisation by inter-signal timing adjustment

摘要

A semiconductor device system comprises a driving-end semiconductor device outputting a clock and a plurality of signals output in synchronism with this clock and a receiving-end semiconductor device receiving the said clock and the plurality of output signals as a plurality of input signals. The receiving-end semiconductor device includes a clock generating circuit generating an internal clock on the basis of the received clock; a plurality of input circuits 53-o to 53-n for receiving the plurality of input signals and latching them in synchronism with a plurality of input timing clocks respectively generated on the basis of the internal clock; a plurality of input timing adjusting circuits 54-o to 54-n receiving the internal clock and outputting the plurality of input timing clocks for adjusting the phases of the plurality of input timing clocks; and an inter-signal timing adjusting circuit 56 for detecting the phase difference between the output signals of the plurality of input circuits and adjusting the output signals in phase with each other.