| 摘要 |
PURPOSE: A semiconductor memory circuit is provided to process in parallel both of a lower decoder and a column decoder by simultaneously enabling all word lines and bit lines to store same external data at all the memory cells. CONSTITUTION: A column test mode flag generating part(8) enables a particular memory cell of a memory cell part to store data or to output stored data according to output signals of lower decoder(3) and column decoder(4) so that all of bit lines of the memory cell part are enabled according to a test mode command of user, wherein the output signals are output by decoding each of lower and column addresses. A lower test mode flag generating part(9) enables all of bit lines of the memory cell part according to the test mode command of user. The lower decoder comprises first to fourth pre-decoders and a plurality of NAND gates, wherein the pre-decoders receive the output signal of the lower test mode flag generating part through a plurality of switches and receive directly a particular lower address to decode the received signals to output pre-decoding signals of each four bits, the gates combine the pre-decoding signals to output them through word lines.
|
