| 摘要 |
A dynamic logic circuit (16) operable in an active mode and in a power down mode, where the active mode comprises a precharge phase and an evaluate phase. The dynamic logic circuit comprises a precharge node (18PN) coupled to be precharged to a precharge voltage (VDD) during the precharge phase and operable to be discharged during the evaluate phase. The dynamic logic circuit further comprises a conditional series discharge path connected to the precharge node and comprising a plurality of transistors (18L, 18DT, 20SDVN) operable to conditionally couple the precharge node to a voltage different than the precharge voltage. Further, the dynamic logic circuit comprises an output inverter (18INV) having an input connected to the precharge node and comprising a plurality of transistors (18INVP, 18INVN) for providing an output signal representative of a voltage at the precharge node during the evaluate phase. Still further, the dynamic logic circuit comprises a precharge transistor (18PT) operable to be enabled during the power down mode and having a source/drain conductive path for coupling the precharge voltage to the precharge node during the precharge phase.
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