发明名称 |
Semiconductor memory device |
摘要 |
The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.
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申请公布号 |
US6246620(B1) |
申请公布日期 |
2001.06.12 |
申请号 |
US20000533759 |
申请日期 |
2000.03.23 |
申请人 |
FUJITSU LIMITED |
发明人 |
FUJIOKA SHINYA;TAGUCHI MASAO;FUJIEDA WAICHIROU;SATO YASUHARU;SUZUKI TAKAAKI;AIKAWA TADAO;NAGASAWA TAKAYUKI |
分类号 |
G11C7/06;G11C7/10;G11C7/12;G11C8/00;G11C8/08;G11C8/10;G11C11/408;G11C11/4091;G11C11/4094;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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