| 摘要 |
The present invention provides a multi-value DRAM that does not require additional surface area, has a low cost, and has a good yield. A 4-value memory cell is disposed at the intersection of a word line WL and sub-bit lines BLNx0. A potential corresponding to 11, 10, 01, and 00 is written to the dunmmy cell disposed at the intersection of the sub-bitline connected to the dummy word lines DWLN and DWLT and the SSAs 31 and 32. The SSA30 outputs the data in the memory cell and the reference levels 0x and 1x on the sub-bit lines BLTx0 to the main bit lines GBLN0 and GBLT0. The SSA31 balances the potentials of the dummy cell connected to both dummy word lines and outputs the reference levels 11 and 10 to the main bit line GBLN4. Similarly, the SSA32 balances the potentials of both dummy cells, and outputs the reference levels 01 and 00 to the main bit line GBLT4. The MSA 33 discriminates the upper bit UPBIT and the lower bit LWBIT of the data based on the potentials on the 4 main bit lines.
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