发明名称 DEVICE AND METHOD FOR PROCESSING LOGIC SIMULATION
摘要 PROBLEM TO BE SOLVED: To accelerate a logic simulation by preventing the occurrence of an unwanted event inside a logic block corresponding to a logic block in a wait state concerning an event-driven simulator. SOLUTION: Concerning the event-driven type logic simulator, the logic block in the wait state of stabilizing an internal state unless an entry from the outside is changed is detected and concerning the logic block in the wait state, the supply of a clock entry from the outside is stopped. Among the logic blocks in the clock entry stop state, a logic block to transit from the wait state to the other state is detected. Concerning the detected logic block to transit from the wait state to the other state, the supply of the clock entry from the outside is restarted.
申请公布号 JP2001155047(A) 申请公布日期 2001.06.08
申请号 JP19990335859 申请日期 1999.11.26
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YONEDA KEI
分类号 G01R31/28;G06F17/50;(IPC1-7):G06F17/50 主分类号 G01R31/28
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