发明名称 METHOD AND SYSTEM FOR CONTROLLING INDUCTIVE CLOCK IN SYNCHRONOUS OPTICAL COMMUNICATION DEVICE
摘要 PURPOSE: A method and a system for controlling an inductive clock in a synchronous optical communication device are provided to operate a system clock and an inductive clock respectively by using a timing signal. CONSTITUTION: A synchronous source operating system is formed with a control portion(505), the first clock generation portion(501), the second clock generation portion(502), and a DPPLL(503). The third clock selection portion controls the first and the second external clocks(ELK1,ELK2), an E line clock(ELK), a W line clock(WCLK), an internal clock(CLK) according to a control operation of the control portion(505). A PLL(Phase Locked Loop)(507) generates a stable output by locking a clock selected from the third clock selection portion(506). A bidirectional buffer outputs the stable output of the PLL(507) to the first and the second clock output ports(ECOP1,ECOP2) or the first and transfer an input of the second external input ports(ECIP1,ECIP2) to the first clock selection portion(501).
申请公布号 KR100299283(B1) 申请公布日期 2001.06.07
申请号 KR19980012221 申请日期 1998.04.07
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 CHOI, SEUNG GWAN
分类号 H04L7/04;(IPC1-7):H04L7/04 主分类号 H04L7/04
代理机构 代理人
主权项
地址