| 摘要 |
<p>A pipelined data path architecture (300) for use, in one embodiment, in a multimedia processor. The data path architecture requires a maximum of two execution pipestages to perform all instructions including wide data format multiply instructions and specially adapted multimedia instructions, such as the sum of absolute differences (SABD) instruction and other multiply with add (MADD) instructions. The data path architecture includes two wide data format input registers (310, 312) that feed four partitioned 32x32 multiplier circuits (314). Within two pipestages, the multiply circuit can perform one 128x128 multiply operation, four 32x32 multiply operations, eight 16x16 multiply operations or sixteen 8x8 multiply operations in parallel. The multiply circuit contains a compressor tree which generates a 256-bit sum (358) and a 256-bit carry (352) vector. These vectors are supplied to four 64-bit carry propagate adder circuits (340) which generate the multiply results.</p> |
