| 摘要 |
A memory system which includes apparatus for efficiently performing parallel testing of the integrity of the memory cells contained in multiple memory devices. Each memory device or system is placed into a mode in which a desired test pattern is automatically written to each memory cell in each device. It is then verified that the data was written with the proper threshold voltage margin. The memory cells in each array are stepped through, address by address, and the data corresponding to the test pattern is written to each cell and then verified. After verification of the operation for a block of cells, a status bit is set to reflect successful completion of the test pattern write operation for the memory block.
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