| 摘要 |
PURPOSE: A command decoding device is provided to perform a repetitious command smoothly and embody a simple hardware. CONSTITUTION: The first flip-flop(2) receives a command from a program data bus(PDB) and receives an output signal of an AND gate to a clock signal. The first multiplexer(4) is connected to the first flip-flop(2) and selectively outputs a program data bus(PDB) signal including a command selectively, an one-cycle delayed command and a returned signal of a repetitious command from the first flip-flop(2) in accordance with a control signal being supplied. A PLA(Program Logic array)(10) is connected to the first multiplexer(4) and decodes a command in accordance with the command being supplied and generates a control signal. An FSM(finite state machine)(16) is connected to the PLA(10) and receives the current command type, a previous state, and a repeating counter flag, and decides a state. The second flip-flop(6) is connected to the first multiplexer(4). The second multiplexer(14) selectively outputs a reset initial value for initializing a system on accordance with a logical value of a reset signal and a control signal from the PLA(10). A zero detector(12) receives a repeating counter and supplies the repeating counter flag having a specific logical value to the PLA(10) and the FSM(16) when the repeating counter value is '0'. The third flip-flop is provided for synchronizing an input of the PLA(10).
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