| 摘要 |
The present invention provides a single-event upset (SEU) hardened integrated circuit (20, 100, 120). The integrated circuit includes an SEU hardened asymmetric bi-stable CMOS latch (22, 22A, 22B) having a first logic state (82, 84) and a second logic state (86, 88). A supply voltage (80) is operably coupled to the asymmetric bi-stable latch (22, 22A, 22B), where upon activation of the supply voltage (80) the asymmetric bi-stable latch (22, 22A, 22B) is always set to the first logic state (82, 84). A switch (36) may be provided for changing the latch (22, 22A, 22B) from the first logic state (82, 84) to the second logic state (86, 88).
|
