| 摘要 |
PROBLEM TO BE SOLVED: To improve performance such as processing capability by closely synchronizing both arithmetic operations. SOLUTION: A computer system is provided with a single chip microcomputer having a central processing unit(CPU), a memory device connected with the CPU, and an interface 56 deformed so that the CPU can be connected with a floating point instruction processor (FPU) 54 and an FPU present signal connected from the interface 56 to the CPU, and a CPU present signal having a first state indicating the existence of an FPU in the single chip microcomputer to the CPU and a second state indicating the non-existence of any FPU in the single chip microcomputer to the CPU. Then, the single chip microcomputer transmits plural floating point instructions across the interface to an FPU 54 in response to the first state of the FPU present signal, and traps the plural floating point instructions in response to the second state of the signal.
|
