| 摘要 |
A high performance random access memory integrated circuit is disclosed in several embodiments, along with various embodiments of associated supporting circuitry, which offers significant power savings in read operations. The integrated circuit is capable of retrieving data words from a memory array either one data word in a single clock cycle or more than one data word in a single clock cycle. For random memory reads, retrieving one data word from the memory array in a clock cycle where the memory array is accessed in response to each read request saves power over retrieving more than one data word from the memory array in the clock cycle. Conversely, if read requests are burst requests (i.e., a first read request immediately followed by advance requests), power is saved by retrieving more than one data word in a clock cycle where the memory array is accessed.
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