发明名称 DATA PATH DESIGNING DEVICE AND LIBRARY THEREFOR
摘要 PROBLEM TO BE SOLVED: To improve the problem that the same logic has the same transistor constitution, is constituted of a library having the same transistor size ratio and it is difficult to automatically develop a data path having the minimum delay in a data path designing device using the self base library. SOLUTION: This device has a selector circuit assigning means 111 for virtually applying timing analysis to a net list prepared by a logic synthesizing means 121, analyzing a delay to the input on the control side of a selector circuit provided inside and a delay to the data input of the selector circuit and assigning the selector circuit of the light input load of a control signal when the delay to the control input side is greater or assigning the other selector circuit when the delay to the data input side is greater. Thus, the delay time from the control signal input can be improved and a further accelerated data path can be developed.
申请公布号 JP2001147949(A) 申请公布日期 2001.05.29
申请号 JP19990329505 申请日期 1999.11.19
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MIYOSHI AKIRA;ARIGA YOSHITOSHI
分类号 H01L21/82;G06F17/50;(IPC1-7):G06F17/50 主分类号 H01L21/82
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