| 摘要 |
PROBLEM TO BE SOLVED: To perform access at high speed, without causing delay in operation caused by the read operation of the same data or precharge operation of a bit line at both a hit, when the same word line address is accessed and miss hit. SOLUTION: Concerning a DRAM in 2Tr1C configuration, an address is latched by an address latch circuit 3 in advance, a word line 9a on the side of Aport corresponding to that address is activated, and data corresponding to a sense amplifier 7a are latched. In a comparator circuit 4, a following input address is compared with the above latched address and when both the addresses are coincident, the data latched by the sense amplifier 7a are read by a column decode circuit 6a. When both the addresses do not match, on the other hand, ordinary data read operation is performed from the side of other Bport different from the Aport, where the data are latched, and on the side of the Aport, the precharge operation of the bit line is performed at the same time. |
