摘要 |
<p>PROBLEM TO BE SOLVED: To reduce power consumption, to stabilize an operation and to take out an ideal phase position signal. SOLUTION: A timing generation circuit 10 receiving an outer reference clock signal EX-CK and generating an origination control signal, plural phase position bestowal circuits 21 inputting an outer trigger EX-T and the origination control signal, storing an origination control signal phase position when the outer trigger EX-T is added and outputting an intermittent phase matching signal whenever it becomes the stored phase position, an OR gate which logic- synthesizes the plural intermittent phase matching signals and outputs a phase matching signal PHS, an OR gate 12 inputting the phase matching signal PHS and the outer trigger EX-T and generating and outputting a phase position signal PH-T and a circuit D-FF outputting an intermittent phase matching signal PH in a phase position which is prior to the phase position stored by the phase position bestowal circuit by delay time peculiar to the circuit, which is previously assumed, and DELAY switch SWs are installed.</p> |