| 摘要 |
<p>A device (20) for performing a consecutive clear bits count on an operand with an offset includes a plurality of logic circuits (22a-h), each associated with a prioritized portion of the operand. Each logic circuit (22a-h) activates an all-zero signal when its respective portion of the operand consists of all zeros, performs a leading zero count on its respective portion of the operand, and generates a leading zero signal by offsetting its leading zero count with a first portion of the offset. Also, a priority encoder (24) generates a signal encoding the priority of the highest priority inactive all-zero signal, and muxes (26, 28) select first and second portions of the leading zero signal associated with the highest priority inactive all-zero signal as a first portion of the consecutive clear bits count and a carryout selector signal, respectively, in accordance with the priority encoded signal. Further, adders (32, 34) generate a no-carryout signal by offsetting the priority encoded signal with a second portion of the offset, and generate a carryout signal by offsetting the priority encoded signal with the second portion of the offset and adding one. A mux (30) then selects one of the no-carryout and carryout signals as a second portion of the consecutive clear bits count in accordance with the carryout selector signal.</p> |
