| 摘要 |
PURPOSE: A semiconductor memory device is provided to prevent exposure of a pattern in a planarization process by forming a test pattern region on a region parallel to a peripheral circuit region. CONSTITUTION: A multitude of die(11) is formed on a wafer. Each die(11) is separated by a scribe line(17). Each die(11) is divided into a memory cell array region(12), a peripheral circuit region(13), and a test pattern region(14). A multitude of memory cell is formed in the memory cell array region(12). A data input/output circuit such as a sub word line drive, an X-decoder, and a Y-decoder and a power supply circuit such as a charge pump are formed on the peripheral circuit region(13). A multitude of test pattern is formed on the test pattern region(14). The peripheral circuit region(13) is arranged in a center portion of the memory cell array region(12). The test pattern region(14) is formed at both sides of the dies(11).
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