| 摘要 |
<p>A synchronous LSI memory device, comprising cell blocks (CB) each having a plurality of memory cells; and a data register (WRITE REGISTER) for acquiring externally input data applied to first terminals (DQ) in synchronism with a clock signal (CLK), said data register being provided with inputting registers (WRITE REGISTER) having a plurality of bits and connected to the respective first terminals; and when data are inputted, the inputting registers being controllable in a first operation according to which the respective plurality of bits are set alternately to data input status, or in a second operation according to which the respective plurality of bits are switched in sequence. <IMAGE></p> |
