发明名称 DUAL PORT RAM
摘要 PURPOSE: A dual port RAM(Random Access Memory) is provided to make easy debugging of a high level and prevent a misoperation by outputting an address competition status to an outside and performing a writing operation according to a condition. CONSTITUTION: The dual port RAM includes a cell array(100), the first and second address buffers(110,111), an address comparator(170), the first and second decoders(120,121), the first and second word line drivers(130,131), the first and second column selectors(140,141), the first and second sense amplifiers(150,151), the first and second output buffers(160), an input data comparator(180), and a column controller(190). The cell array consists of a plurality cells storing data. The address buffers buffer input address signals in response to the first and second chip enable bar signals. The address comparator compares the first and second address signal outputted from the address buffers and outputs an address comparison signal. The decoders decode address signal outputted from the address buffers in response to an error signal. The word line drivers enable word lines in the cell array in response to decoded signals outputted from the decoders. The column selectors enable columns in the cell array in response to the decoded signals outputted from the decoders. The sense amplifiers sense data of cells selected by the column selector and word line drivers in response to the first and second writing control signals or store the data in the selected cells. The output buffers buffer input data in response to an output enable signal and output to the sense amplifiers or buffer data sensed by the sense amplifiers and output as external output signals. The input data comparator compares an input data buffered by the output buffers and outputs an input data comparison signal. The column controller receives output signals of the address comparator and input data comparator, controls the operation of the decoders by detecting an error, and controls the operation of the sense amplifiers in response to the detected error signal and the writing enable bar signals.
申请公布号 KR20010037977(A) 申请公布日期 2001.05.15
申请号 KR19990045764 申请日期 1999.10.21
申请人 HYNIX SEMICONDUCTOR INC. 发明人 LEE, JUNG YONG
分类号 G11C11/407;(IPC1-7):G11C11/407 主分类号 G11C11/407
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