CIRCUIT OF CORRECTING DELAY TIME OF CLOCK SIGNAL

摘要

PURPOSE: A delay time correcting circuit is provided to be capable of realizing an exact signal matching by setting a reference clock signal line and a delay clock signal line in the same layer circumstance. CONSTITUTION: A digital lock loop(DLL)(200) generates a reference clock signal(RCK) in response to an externally applied clock signal and a delay clock signal(CLK_A) delayed with regard to the reference clock signal. The second local driver(22) and the second input/output control part(102) are used to match a transfer path of the reference clock signal. A buffer(26) of a clock buffer(204) generates the reference clock signal(RCK), a buffer(24) thereof generates the delay clock signal(CLK_A). The reference clock signal from the buffer(26) is applied to the first local driver(220) through a reference clock signal line(230), and the delay clock signal from the buffer(24) is applied to the second local driver(22) through a delay clock signal line(210). The reference clock signal line is realized in the same layer as the delay clock signal line(210).