Integrated circuit delay lines having programmable and phase matching delay characteristics

摘要

Programmable delay lines include a delay circuit having an input and a plurality of outputs which each provide a respective delayed version of a periodic input signal provided to the input. A delay switch is also provided to pass at least one of the plurality of outputs of the delay circuit to a switch output, in response to a digital control signal (P1-Pn). A preferred phase comparing circuit is also provided. This phase comparing circuit compares the input signal against the delayed versions of the input signal (at the plurality of outputs) and generates a digital phase signal (F1-Fn) that identifies which of the delayed versions of the input signal is in-phase with the input signal. The programmable delay line also includes a pointer which generates the digital control signal in response to the digital phase signal and a plurality of pointer control signals (S0, S1 and WS).