发明名称 Semiconductor memory device with high data access speed
摘要 A semiconductor memory device, comprising: address input means for receiving an external column address signal; address buffer means for converting the external column address signal through address input terminal into an internal column address signal; address predecoder means for receiving the internal column address signal from the address buffer means and predecoding it to generate global column address signals; column redundancy fuse array means for generating a first detection signal indicating whether the global column address signals are normal address signals or spare address signals and a second detection signal indicating that the defects are fully repaired with any one of a column redundancy circuit or a row redundancy circuit; redundancy selection means for generating a spare column enable signal or a normal column enable signal in accordance with the first detection signal; address block repeater means for directly providing the global column address signals from the predecoder as column address signals in accordance with the second detection signal from the redundancy fuse array means regardless of the normal column enable signal, or for delaying the global column address signals from the predecoder for a selected time in accordance with the normal column enable signal and providing them as the column address signals; column main decoder means for decoding the column address signals from the address block repeater means to generate a column selection signal; and spare column decoder means for generating a spare column selection signal by the spare column enable signal from the redundancy selection means.
申请公布号 US6233183(B1) 申请公布日期 2001.05.15
申请号 US20000539827 申请日期 2000.03.31
申请人 HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. 发明人 KIM YONG KI;JEONG CHEOL WOO
分类号 G11C11/408;G11C29/00;(IPC1-7):G11C7/00 主分类号 G11C11/408
代理机构 代理人
主权项
地址