| 发明名称 |
Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit |
| 摘要 |
An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles.
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| 申请公布号 |
US2001000995(A1) |
申请公布日期 |
2001.05.10 |
| 申请号 |
US20000747790 |
申请日期 |
2000.12.22 |
| 申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
PHELAN CATHAL |
| 分类号 |
G11C5/14;(IPC1-7):G11C8/00 |
主分类号 |
G11C5/14 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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