| 摘要 |
PURPOSE: A column selection circuit of a memory device is provided to reduce a chip layout area by integrating a read bus and a write bus as one body and removing a column selector for a writing operation, and improves a sensing speed of a bit line. CONSTITUTION: A memory cell(204) stores a data loaded on bit lines(BL,/BL) by a word line signal(WL) in case of a write operation, and transmits a stored data to the bit lines(BL,/BL) by a word line signal(WL) in a read operation. A bit line equalizer(203) equalizes the bit lines(BL,/BL) with a bit line equalizing voltage(VBL) when an equalizing signal(EQ) is enabled at initial operation of the read/or write operation. A bit line sense-amp(205) amplifies the data loaded on the bit lines(BL,/BL) from the memory cell by the word line signal(WL) in case of a read operation. A sense-amp controller(206) operates the bit line sense-amp(205) by control signals(SO,/SO) in case of a read operation. A precharge part(201) precharges data lines(DBi,/DBi) by a transmission data from the bit lines(BL,/BL) or an external transmission data. In case of a write operation, a column selector(202) transmits the data loaded on the data lines(DBi,/DBi) to the bit lines(BL,/BL) when a column selection signal(Y) is enabled after the bit lines(BL,/BL) are equalized. In case of read operation, the column selector(202) transmits the data loaded on the bit lines(BL,/BL) to the data lines(DBi,/DBi) when a column selection signal(Y) is enabled after the data loaded on the bit lines(BL,/BL) are amplified by the bit line sense-amp(205).
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