| 摘要 |
PURPOSE: A negative delay circuit for a DDR SRAM is provided, which is suitable for a DDR SDRAM and suffer from no voltage, temperature, and process variations. CONSTITUTION: A plurality of unit delays(200,210,220, ...) are connected to a delay. Each of the unit delays consists of a NAND gate(NAND) and an inverter(I). The delay delays an input clock signal(CLK). The unit delay(200) delays an output of the delay(100), the unit delay(210) delays an output of the unit delay(200), and the unit delay(220) delays an output of the unit delay(210). The first flip-flop(300) transfers a delayed clock signal from the delay, the second flip-flop(310) transfers a delay clock signal from the first unit delay(200). The flip-flops operate in synchronization with a clock signal(CLKI).
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