发明名称 Display device comprising a function for automatically adjusting phase of sampling clocks
摘要 <p>In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an AID converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum. With this operation, the sampling phase can be automatically adjusted to the optimum value when the video signal is converted to digital data. &lt;IMAGE&gt;</p>
申请公布号 EP1096684(A2) 申请公布日期 2001.05.02
申请号 EP20010100167 申请日期 1996.07.25
申请人 HITACHI, LTD. 发明人 NAKA, KAZUTAKA;MARUYAMA, ATSUSHI;URATA, HIROYUKI;IWANAGA, MASAAKI
分类号 G06F1/10;G09G5/18;H03L7/081;H03L7/091;H03L7/199;H04N5/04;H04N5/12;H04N5/20;H04N5/66;H04N9/64;(IPC1-7):H03L7/085 主分类号 G06F1/10
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