| 摘要 |
PURPOSE: A memory module having a module control circuit is provided to construct 4Mx64 module with 16M DRAM(1K Refresh,x16) by including a module control circuit, and reduces an operation current by reducing the number of operation devices. CONSTITUTION: A module control circuit includes a decoder, a latch, CBR detector. The decoder decodes 11th and 12th address signals(A10,A11). The latch latches output signals(iA0-iA3) of the decoder according to a row address strobe signal(/RAS). The CBR detecto outputs a control signal(/RAS0-/RAS3) according to one of output signals(iRAS0-iRAS3) of the latch and column address strobe signals(/CAS0-/CAS7) or the row address strobe signal(/RAS). A memory module includes many DRAMs(M31-M46) that are selected by the control signals(/RAS0-/RAS3) from the module control circuit(100), and perform a data write/read operation according to the address signals(A0-A9), a write enable signal(/WE), an output enable signal(/OE), and the column address strobe signal(/CAS0-/CAS7).
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