| 摘要 |
A system and method for detecting phase lock in a phase locked loop (PLL) which determines a phase of an oscillating frequency by detecting a phase of a frequency of a voltage controlled oscillator including a multi-detection circuit for generating a locked information signal having N bits by comparing a phase difference between the input reference frequency and the fed-back oscillating frequency to determine a logical up/down signal for charging/discharging during the up/down interval, and when the charge voltage is predicted to equal a reference voltage representing a signal which is K times the reference frequency, for comparing to the set reference frequency in turn to add or subtract from the determined value which is divided by four from the reference frequency, and also includes a current controller for determining input current of a charging pump based on the locked information signal having N bits. As a result, the bandwidth is controlled such that in an unlocked condition, faster tracking is possible, and in a locked condition, phase loss due to jittering and switching can be minimized. Finally, current consumption due the large current input in the charging pump can be significantly reduced.
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