| 摘要 |
The present invention discloses an EPLD cell includes a semiconductor substrate, tunnel buried layer, control gate, and floating gate. The tunnel buried layer and control gate, which has a three-dimensional contour, are formed under the surface of semiconductor substrate by implanting N-type dopant. The floating gate formed completely over the tunnel buried layer and partially over the control gate, is insulating from them by oxide layers. Because of the three-dimensional contour of control gate, the overlapped area between the floating gate and control gate could be increase without expanding horizontal area of the cell. Therefore, the efficiency of the cell can be improved without degrading the integration in applying the cell.
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