| 摘要 |
<p>PROBLEM TO BE SOLVED: To eliminate the need for high-speed circuit elements by giving a frequency approximating that of a feedback clock to a master clock of a digital PLL. SOLUTION: Signals 103, 105, and 107 obtained by delaying a master clock 101 are generated by delay element 102, 104, and 106 connected in series. If a feedback clock 109 has a phase delayed behind a reference clock 110, this phase relation is detected by a phase comparator 111, and a multiplexer 108 is so instructed that it may select the signal 103 which has a phase leading the signal 105 selected at present. As a result, the phase of the feedback clock 109 approaches that of the reference clock. This process is sequentially repeated to lock the feedback clock to the phase and the frequency of the reference clock.</p> |
