发明名称 |
LAYERED CAPACITOR, WIRING BOARD AND HIGH FREQUENCY CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To reduce the serial equivalent inductance (ESL) of a layered capacitor. SOLUTION: First and second side face terminal electrodes 12 and 13 are alternately arrayed on the four sides 4-7 of a capacitor main body 8, and first and second main surface terminal electrodes 14 and 15 are arranged on the main surface 2. First and second internal electrodes facing each other provided inside the capacitor main body 8 are respectively electrically connected to the first and second side terminal electrodes 12 and 13 at respective edges and electrically connected to the first and second main surface terminal electrodes 14 and 15 through via hole conductors. In such a manner, a current flowing in this capacitor 1 is turned to various directions, a current length is shortened and thus the ESL is reduced. |
申请公布号 |
JP2001118746(A) |
申请公布日期 |
2001.04.27 |
申请号 |
JP19990294908 |
申请日期 |
1999.10.18 |
申请人 |
MURATA MFG CO LTD |
发明人 |
KURODA TAKAKAZU;TANIGUCHI MASAAKI;NAITO YASUYUKI;HORI HARUO;KONDO TAKANORI |
分类号 |
H01G4/12;H01G4/232;H01G4/30;H01L23/12;H05K1/02;H05K1/18 |
主分类号 |
H01G4/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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