发明名称 METHOD FOR MANUFACTURING INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a method for forming a flat inter-level dielectric layer of low k, which comprises an FSG layer of HDP-CVD which protects a conductive layer from fluorine. SOLUTION: A method is comprised where a conductive layer is deposited near a semiconductor substrate, and the conductive layer is formed multiple stages, in which a plurality of conductive lines comprising gap are formed. The conductive layer is a metal layer which comprises at least either aluminum or copper. An FSG layer is formed on the conductive layer which is patterned by a high density plasma CVD, filling the gap between conductor lines. Furthermore, a method is comprised where the FSG layer is chemically-mechanically polished, and an undoped oxide layer is deposited over the FSG layer. The peak of FSG layer, corresponding to the width of a conductive metal line, is reduced by a step of CMP. Thus, a following conductive layers that follow are protected from being exposed to fluorine due to the FSG layer.
申请公布号 JP2001118928(A) 申请公布日期 2001.04.27
申请号 JP20000246203 申请日期 2000.08.15
申请人 LUCENT TECHNOL INC 发明人 ALVARO MAURY;ABDELGADIR MAHJOUB ALI
分类号 H01L23/522;C23C14/08;C23C14/58;H01L21/02;H01L21/28;H01L21/304;H01L21/316;H01L21/3205;H01L21/768;H01L23/532;H01L29/51;(IPC1-7):H01L21/768 主分类号 H01L23/522
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