| 摘要 |
PROBLEM TO BE SOLVED: To solve clock skew violation by adjusting the wiring length of a clock path, without changing the logic configuration nor increasing the area, so that the propagation delay time is adjusted. SOLUTION: A clock skew value, which is required from a clock skew value input means 0101, is inputted, and the propagation delay time for clock path is calculated with a propagation delay time calculating means 0102. Based on the propagation delay time, a clock path violating with respect to a clock skew value requirement is detected with a clock path propagation delay time violation detecting means 0103, and the detected clock path as well as the register coordinates connected to it are detected with a coordinate detecting means 0104. Based on the coordinate, a clock path and each register coordinate with which a clock skew is accommodated within a required range are calculated with a clock skew optimization coordinate calculating means 0105, and arrangement/wiring is performed by an arrangement/wiring means 0105, based on that coordinate.
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