发明名称 TEST CIRCUIT, TEST CIRCUIT GENERATING DEVICE, TEST CIRCUIT GENERATING METHOD, AND ITS RECORDING MEDIUM
摘要 PROBLEM TO BE SOLVED: To provide a test circuit for an integrated circuit device with shortened testing time, reduced pattern length, and reduced number of external terminals. SOLUTION: This test circuit is set between first and second circuits to be tested for performing a test to the first and second circuits to be tested. It selects a first output signal outputted from the first circuit to be tested or a second output signal outputted from the second circuit to be tested or a test signal on the basis of a test mode signal inputted from the outside, temporarily stores the selected signal as data, selects the temporarily stored data or the second output signal on the basis of a second test mode signal and sets it to the first circuit to be tested, and selects the temporarily stored data or the first output signal on the basis of a third test mode signal and outputs it to the second circuit to be tested.
申请公布号 JP2001116804(A) 申请公布日期 2001.04.27
申请号 JP19990297453 申请日期 1999.10.19
申请人 NEC CORP 发明人 NAKAMURA YOSHIYUKI
分类号 G01R31/28;G01R31/317;G01R31/3185;G06F11/22 主分类号 G01R31/28
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